regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi lsis m5m5v108dfp,vp,kv -70hi 1048576-bit(131072-word by 8-bit)cmos static ram 7th.july.2000 ver. 1.1 nc : no connection description features type name access time (max) active (max) stand-by (max) power supply current the m5m5v108dfp,vp,kv are a 1048576-bit cmos static ram organized as 131072 word by 8-bit which are fabricated using high- performance triple-polysilicon and double metal cmos technology. the use of thin film transistor (tft) load cells and cmos periphery result in a high density and low power static ram. they are low standby current and low operation current and ideal for the battery back-up application. the m5m5v108dvp,kv are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(smd). package application small capacity memory units directly ttl compatible : all inputs and outputs easy memory expansion and power down by s 1 ,s 2 data hold on +2v power supply three-state outputs : or - tie capability oe prevents data contention in the i/o bus common data i/o m5m5v108dfp,vp,kv-70hi 70ns 5ma 2.7~3.6v 24? (1mhz) v cc m5m5v108dfp 32pin 525mil sop m5m5v108dvp,rv 32pin 8 x 20 mm tsop m5m5v108dkv,kr 32pin 8 x 13.4 mm tsop 1 2 2 pin configuration (top view) a 11 a 9 a 8 a 13 w s 2 a 15 v cc nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 oe a 10 s 1 dq 8 dq 7 dq 6 dq 5 dq 4 gnd dq 3 dq 2 dq 1 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 m5m5v108dvp,kv outline 32p3h-e(vp), 32p3k-b(kv) nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 gnd v cc a 15 s 2 w a 13 a 8 a 9 a 11 oe a 10 s 1 dq 8 dq 7 dq 6 dq 5 dq 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 outline 32p2m-a address input chip select input write control input address inputs output enable input address input chip select input data inputs/ outputs address inputs data inputs/ outputs
mitsubishi lsis m5m5v108dfp,vp,kv -70hi 1048576-bit(131072-word by 8-bit)cmos static ram 7th.july.2000 ver. 1.1 function block diagram the operation mode of the m5m5v108d series are determined by a combination of the device control inputs s 1 ,s 2 ,w and oe. each mode is summarized in the function table. a write cycle is executed whenever the low level w overlaps with the low level s 1 and the high level s 2 . the address must be set up before the write cycle and must be stable during the entire cycle. the data is latched into a cell on the trailing edge of w,s 1 or s 2 ,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. the output enable input oe directly controls the output stage. setting the oe at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. a read cycle is executed by setting w at a high level and oe at a low level while s 1 and s 2 are in an active state(s 1 =l,s 2 =h). when setting s 1 at a high level or s 2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high- impedance state, allowing or-tie with other chips and memory expansion by s 1 and s 2 . the power supply current is reduced as low as the stand-by current which is specified as i cc3 or i cc4 , and the memory data can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation in the non- selected mode. s 1 s 2 w oe mode dq i cc l l h h h h l h non selection write read high-impedance din dout active stand-by non selection high-impedance high-impedance active active stand-by function table l h l x h x x x x l x x 2 clock generator 131072 words x 8 bits ( 512 rows x128 columns x 16blocks ) 21 22 23 25 26 27 28 29 13 14 15 17 18 19 20 21 5 30 6 32 8 29 22 30 24 32 16 24 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 w s1 s2 oe v cc gnd (0v) * pin numbers inside dotted line show those of tsop * * data inputs/ outputs write control input chip select inputs output enable input address inputs a3 a2 a5 a6 a7 a12 a14 a16 a15 a13 a8 a9 a11 a1 a0 a10 a4 7 10 3 4 5 6 7 10 9 11 12 13 14 15 18 17 2 31 2 3 4 28 27 26 1 25 20 19 11 12 31 23 16 8 note 1: "h" and "l" in this table mean vih and vil, respectively. 2: "x" in this table should be "h" or "l".
mitsubishi lsis m5m5v108dfp,vp,kv -70hi 1048576-bit(131072-word by 8-bit)cmos static ram 7th.july.2000 ver. 1.1 absolute maximum ratings capacitance symbol parameter test conditions pf pf unit max 8 10 typ min limits v i =gnd, v i =25mvrms, f=1mhz v o =gnd,v o =25mvrms, f=1mhz input capacitance output capacitance c i c o parameter supply voltage input voltage output voltage power dissipation operating temperature storage temperature unit v v v mw ? ? conditions with respect to gnd ta=25? 700 ?40~85 ?65~150 ratings symbol v cc dc electrical characteristics (ta=?40~85?, vcc=2.7~3.6v, unless otherwise noted) symbol parameter v v v max typ limits min test conditions unit v ? ?0.3*~4.6 ?0.3*~vcc + 0.3 (ta=?40~85?, unless otherwise noted) 0~vcc * ?.0v in case of ac ( pulse width 30ns ) note 3: direction for current flowing into an ic is positive (no mark). 4: typical value is vcc = 3v, ta = 25? ma * ?.0v in case of ac ( pulse width 30ns ) ? ? ma v vcc + 0.3 0.6 2.0 ?.3* 2.4 0.33 stand-by current 0.4 ? active supply current active supply current vcc ?0.5 ? 35 v ih v il v oh1 v oh2 v ol i i i o i cc1 i cc2 i cc3 i cc4 high-level input voltage low-level input voltage high-level output voltage 1 high-level output voltage 2 low-level output voltage input current output current in off-state stand-by current i oh = ?0.5ma i oh = ?0.05ma i ol = 2ma v i =0~vcc s 1 =v ih or s 2 =v il or oe=v ih v i/o =0~v cc s 1 =v il ,s 2 =v ih , other inputs=v ih or v il output-open(duty 100%) 1) s 2 0.2v other inputs=0~v cc 2) s 1 3 v cc ?.2v, s 2 3 v cc ?.2v other inputs=0~v cc s 1 =v ih or s 2 =v il , other inputs=0~v cc ~25? (max 4.6) 3 ~40? ~70? 1.2 3.6 12 30 5 70ns 100ns 1mhz v i v o p d t opr t stg ~85? 24 -hi
mitsubishi lsis m5m5v108dfp,vp,kv -70hi 1048576-bit(131072-word by 8-bit)cmos static ram 7th.july.2000 ver. 1.1 (2) read cycle (3) write cycle symbol parameter t cr read cycle time address access time unit ns ns ns ns ns ns ns ns ns ns ns ns symbol parameter unit ns ns ns ns ns ns ns ns ns ns ns ns ns limits t a(s1) t a(s2) t a(oe) t dis(s1) t dis(s2) t dis(oe) t en(s1) t en(s2) t en(oe) t v(a) t a(a) limits ac electrical characteristics (ta=?40~85?, unless otherwise noted ) (1) measurement conditions chip select 1 access time chip select 2 access time output enable access time output disable time after s 1 high output disable time after s 2 low output disable time after oe high output enable time after s 1 low output enable time after s 2 high output enable time after oe low data valid time after address 70 70 70 35 25 25 25 70 10 10 5 10 write cycle time write pulse width address setup time address setup time with respect to w chip select 1 setup time chip select 2 setup time data setup time data hold time write recovery time output disable time from w low output disable time from oe high output enable time from w high output enable time from oe low 25 25 70 55 0 65 65 65 30 0 0 5 5 v cc 2.7~3.6v input pulse level v ih =2.2v,v il =0.4v input rise and fall time 5ns reference level v oh =v ol =1.5v output loads fig.1, c l =30pf c l =5pf (for t en ,t dis ) transition is measured ?500mv from steady state voltage. (for t en ,t dis ) ................................. ............... ............. ..... ................... including scope and jig 1ttl c l dq fig.1 output load min max -70hi max min t cw t w(w) t su(a) t su(a-wh) t su(s1) t su(s2) t su(d) t h(d) t rec(w) t dis(w) t dis(oe) t en(w) t en(oe) -70hi 4
mitsubishi lsis m5m5v108dfp,vp,kv -70hi 1048576-bit(131072-word by 8-bit)cmos static ram 7th.july.2000 ver. 1.1 t en (w) read cycle write cycle (w control mode) (4) timing diagrams data valid (note 5) (note 5) t a(a) t a (s1) t v (a) t a (s2) t en (s2) t dis (s1) t dis (s2) t a (oe) t en (oe) t dis (oe) (note 5) (note 5) (note 5) (note 5) t cr t h (d) t su (d) dq 1~8 s 1 t su (s1) s 2 oe t su (s2) t su (a-wh) t en(oe) t dis (oe) (note 5) (note 5) (note 5) (note 5) w t w (w) t rec (w) t su (a) t dis (w) t cw t en (s1) w = "h" level a 0~16 dq 1~8 s 1 s 2 oe a 0~16 stable data in 5
mitsubishi lsis m5m5v108dfp,vp,kv -70hi 1048576-bit(131072-word by 8-bit)cmos static ram 7th.july.2000 ver. 1.1 write cycle ( s 1 control mode) write cycle (s 2 control mode) t su (s1) (note 5) (note 5) t rec (w) t h (d) t cw (note 7) (note 5) (note 5) t su (a) (note 6) t su (d) t h (d) t cw (note 7) (note 5) (note 5) t su (s2) t rec (w) t su (a) (note 6) (note 5) (note 5) t su (d) data in stable data in stable dq 1~8 s 1 s 2 w a 0~16 dq 1~8 s 1 s 2 w a 0~16 note 5: hatching indicates the state is "don't care". 6: writing is executed while s 2 high overlaps s 1 and w low. 7: when the falling edge of w is simultaneously or prior to the falling edge of s 1 or rising edge of s 2 , the outputs are maintained in the high impedance state. 8: don't apply inverted phase signal externally when dq pin is output mode. 6
mitsubishi lsis m5m5v108dfp,vp,kv -70hi 1048576-bit(131072-word by 8-bit)cmos static ram 7th.july.2000 ver. 1.1 v cc = 3v 1) s 2 0.2v, other inputs = 0~3v 2) s 1 3 v cc ?.2v, s 2 3 v cc ?.2v other inputs = 0~3v (ta=?40~85?, unless otherwise noted) (3) power down characteristics s 1 control mode power down characteristics (1) electrical characteristics power down set up time power down recovery time (2) timing requirements (ta=?40~85?, unless otherwise noted ) t su (pd) t rec (pd) symbol parameter ns max typ limits min test conditions unit 0 5 ms 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) s 1 3 v cc - 0.2v v cc s 1 0.2v t rec (pd) 2.7v s 2 0.2v s 2 control mode 2.7v t su (pd) 0.2v v cc s 2 symbol parameter v v max typ limits min test conditions unit ? v 2 0.2 v cc (pd) v i (s1) v i (s2) i cc (pd) power down supply voltage chip select input s 1 chip select input s 2 power down supply current 2.0 7 ~25? ~40? ~70? -hi 1 3 10 v 0.6 vcc(pd) 2.7v vcc(pd) vcc(pd)<2.7v ~85? 20 note 9: on the power down mode by controlling s 1 ,the input level of s 2 must be s 2 3 vcc - 0.2v or s 2 0.2v. the other pins(address,i/o,we,oe) can be in high impedance state.
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